7 Structural Modelling

7 Structural Modeling

By means of struktural modeling the module's internal construction can be described as single sub modules, which are put together. Each sub module can again consist of further such sub modules, and thus a hierarchical structure results. The VHDL description of the lowest hierarchical levels can however no longer be structural modeled, but must be described by means of behavioural modeling.

In the first chapter an example for structural modeling was introduced using a SR flip-flop. This example will be here further examined in order to visualize the basic VHDL constructs for structural modeling such as components, blocks and the GENERATE statement.

A significant fundamental digital circuit is the negative-edge-triggered JK flip-flop, which consists of a SR flip-flop with controlled preparation inputs. A clock component serves to control the negative edge of the clock input.

Figure 7-1: Wiring diagram of a negative-edge-triggered JK flip-flop

An applet should appear here in case your browser supports JAVA !

In the subsequent chapters a description will be given, how the clock component can be built using basic digital components in a structural modeling manner.

von J. Heising
Copyright © 1996 FH-Köln