|
|
|
|
| Contents |
8.1 Signals and Signal Assignment
8.1.1 Event driven Simulation Concept
8.1.2 Signal Assignment
8.1.2.1 Conditional Signal Assignment
8.1.2.2 Selected Signal Assignment
8.1.3 Delay Models
8.1.3.1 Inertial Delay Model
8.1.3.2 Transport Delay Model
8.1.3.3 Reject-Inertial Delay Model
8.2 Concurrent Statements
8.2.1 The Process;
8.2.1.1 WAIT Statement
8.2.2 Further Concurrent Statements
8.3 Examples of complete VHDL Models
8.3.1 The Falling Edge controlled JK-Flipflop
8.3.2 A simple Computer named "TOY"
|
|
von J. Heising Copyright © 1996 FH-Köln |
|