The hardware description language VHDL has found an international recognition as a language for the specification and computer supported simulation of digital hardware. This information system was built due to the increasing significance of the language. It was developed at the department of communicating systems at the Cologne polytechnic in the framework of a thesis. The goal of VHDL-easy is to enable the user independently to get into the foundation of VHDL.

Introduction to VHDL-easy

Further thesis will be offered in the Labor of communicating systems and process automation for the extension of VHDL-easy.

Links to other VHDL resources :

VHDL archive of the Hamburg university

VHDL on-line of the Erlangen university

VHDL course of the Rostock university

VHDL International (VI)

VHDL-Newsnet-FAQs

von J. Heising Copyright © 1996 FH-Köln